1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a ball grid array (BGA) package semiconductor device having a ball shaped contact portion for interfacing with the external circuit.
2. Description of the Related Art
As electronic appliances become smaller, lighter and thinner, the semiconductor devices which form the building blocks of the electronic appliance must also become smaller, lighter and thinner. Accordingly, older semiconductor packaging technologies, for example, dual in-line packages (DIP), small outline with J-leads (SOJ), and quad flat packages (QFP), are being supplanted with newer packaging technologies such as ball grid array (BGA) and chip scale packages (CSP). In these improved BGAs or CSPs, a ball is used instead of a conventional lead to reduce the size of a semiconductor package as much as possible. Investment into research and development to reduce the size of a semiconductor package to the size of a chip continues unabated.
The use of BGA packages using a ball instead of a conventional lead has expanded, including such devices as Rambus dynamic random access memories (RDRAMs). The BGA package connects a pad in a semiconductor device to a ball through a predetermined signal circuit pattern formed on a substrate. Unlike a bonding wire used in a conventional SOJ package, a signal circuit pattern is advantageous in combining a plurality of signal lines or a plurality of power lines.
A CSP semiconductor device employing a conventional BGA package type is disclosed in U.S. Pat. No. 5,920,118.
FIGS. 1A and 1B are a plan view and a sectional view, respectively, of the BGA package semiconductor device described in the above patent. Referring to FIGS. 1A and 1B, the conventional BGA package semiconductor device includes a single layer substrate 110, a semiconductor chip 120 having a plurality of pads 122 positioned along a central axis, a bonding unit 140 between the semiconductor chip 120 and the substrate 110, and a plurality of balls 150 for connection with an external circuit. The substrate 110 has ball mounts 116, on which the balls 150 are mounted along one plane. The ball mounts 116 are connected to the pads 122 of the semiconductor chip 120 through slot 112 via a predetermined signal circuit pattern 114 and bonding wires 130.
However, for a conventional BGA package semiconductor device which is supplied with two or more types of external power, at least two external power supplies need to be separately connected to the device, thereby restricting the combination between the lines of the same power. Accordingly, as shown in FIG. 1A, separated power lines are formed. Since the separated power lines have a narrow gap therebetween, the inductance of a power line increases.
The problems associated with the conventional technology will be described in detail with reference to FIG. 2. FIG. 2 is a detailed diagram illustrating the pattern of one side of the substrate 110 of a conventional BGA package semiconductor device. Referring to FIG. 2, a plurality of pads 122 are arranged in a line along the center of the single layer substrate 110, and the pads 122 are electrically connected to ball mounts (circled portions in FIG. 2) through various thick and thin interconnection lines. The ball mounts labeled VDD are power ball mounts, and the ball mounts labeled VSS are ground ball mounts. The other ball mounts are signal ball mounts.
In such a conventional BGA package semiconductor device, the power ball mounts, the ground ball mounts and the signal ball mounts are arranged in mixed patterns on a surface of a single layer substrate on both sides of a slot formed in the substrate. Therefore, one must be careful that the various interconnections are adequately separated to avoid crossing the various leads in these mixed patterns.
Referring to FIG. 2, note the area denoted by reference numeral 170, where both a power line connected to a power ball mount VDD and a ground line connected to a ground ball mount VSS are routed through between two adjacent signal ball mounts. In such case, the interconnections lines must be narrower, which increases the inductance of the power line, thereby causing reliability problems.
In the area denoted by reference numeral 172, there is shown another problem. Here, the interconnection line is connected between just a single ball mount and a pad, and the interconnection line is not connected to another of the same kind of ball mount. Such an interconnection scheme increases switching noise.
As described above, when various types of interconnection lines are designed on a single layer substrate of a BGA package semiconductor device together with a plurality of ball mounts according to the conventional technology, switching noise may be increased and power reliability may be decreased. Both can lead to an erroneous operation of a semiconductor device.